Nowadays, to achieve low power consumption, an integrated circuit (e.g., Application Specific Integrated Circuit (ASIC), a system-on-chip (SoC) that includes an ASIC, etc.) typically is designed such that portions of the circuit can be selectively powered off based on operational needs. To facilitate selective powering on and off, such an integrated circuit can comprise a plurality of power domains, where circuits associated with a certain power domain can be powered off independently from circuits associated with another power domain.
FIG. 1A illustrates an example of an integrated circuit 100 with multiple power domains. As shown in FIG. 1A, integrated circuit 100 also includes memory block 112 and logic block 114 organized under a power domain 116, memory 122 block and logic block 124 organized under a power domain 126, and memory block 132 and logic block 134 organized under a power domain 136. Memory blocks 112, 122, and 132 can include any kind of on-chip memory such as, for example, static random access memory (SRAM). Logic blocks 114, 124, and 134 can include any kind of circuitry such as, for example, Complementary metal oxide semiconductor (CMOS) circuits.
Integrated circuit 100 also includes a power management unit (PMU) 102, which can also include CMOS circuits and can individually enable (or disable) each of power domains 116, 126, and 136. A power domain enters a power-on state when enabled, and enters a power-off state when disabled. Each of power domains 116, 126, and 136 can be selectively coupled with a voltage rail 150, which can be configured as a power supply. PMU 102 can selectively enable (or disable) the power supply to a particular power domain, by setting a power disable signal (not shown in FIG. 1A) to a certain voltage level. As an illustrative example, when a power disable signal reaches a voltage level that represents a logical “zero,” the power domain coupled with that power disable signal can be enabled.
When the power supply to a power domain is disabled under a power management scheme, the memory and logic blocks of that power domain can also exhibit certain behaviors. For example, the data written in the memory block just prior to the disabling of the power domain will become erased when the power domain is disabled. When the power supply to that power domain is enabled again, before any data is written in the memory block, the initial data in the memory block can be of certain patterns. For example, the initial data in the memory block, after the power domain is enabled, can be all logical “ones” or all “zeros.”
Moreover, the logic blocks can also be controlled to exhibit certain behaviors when the power supply to the associated power domain is disabled under the power management scheme. For example, as shown in FIG. 1A, each power domain can be coupled with a local reset signal and an isolation enable signal. The local reset signal can be configured to set a logic state of some types of logics (e.g., sequential logic, such as flip-flop and latch) to a certain pre-defined state, when the power domain is in the power-off state. The isolation enable signal can be configured to enable one or more isolation cells (“ISO cells”) associated with the power domain. The ISO cells can set a logic state of an input to at least some of the logics (which can include both sequential logic and combination logic) when the power supply to the power domain is disabled. With such an arrangement, the logic state of the logic blocks 114, 124, and 134, when the power supply to the associated power domains are disabled, can become defined, which can minimize the likelihood of unexpected behavior of these logic blocks when their associated power domains transits from a power-off state to a power-on state.
Typically, as shown in FIG. 1B, the isolation enable operation and reset operation at a power domain occur during a power-off sequence, when the power supply to the power domain is still enabled (e.g., where the power disable signal has a low logic state), and the logic blocks of that power domain are still supplied with power. Once the power-off sequence completes, power disable signal can then transit to a high logic state to disable the power supply to the power domain.
Referring back to FIG. 1A, integrated circuit 100 can also receive a system reset signal 152 and a system clock 154. System reset signal 152 can be a signal configured to set all the logics of integrated circuit 100 to one or more logic states. System reset signal 152 typically resets integrated circuit 100 when it is powered up, and is typically inactive when individual power domains enter a power-off state. System clock 154 can be a signal that toggles at a predetermined frequency (e.g., 10 MHz). System clock 154 can be configured to synchronize the operations of some of the logics (e.g., sequential logics) and the memory block among and within the power domains. System clock 154 can also be used by PMU 102 to synchronize the generation of the isolation enable signal, the local reset signal, and the power disable signal. Further, each of power domains 116, 126, and 136 can include a local clock that can be selectively coupled with the system clock 154. PMU 102 can couple a local clock of a power domain to the system clock 154, when the power domain is enabled, and can decouple the local clock from the system clock 154 when the power domain is disabled. When the local clock is decoupled from the system clock 154, it can stop toggling, and power consumption due to switching power can be further reduced. In some cases, the coupling and decoupling of the local clock signal from the system clock 154 can be based on the power disable signal of FIG. 1B.
Some of the behaviors of integrated circuit 100 can be emulated using a field programmable gate array (FPGA), for prototyping and/or validating an ASIC design. An FPGA typically includes an array of programmable logic blocks, which typically includes a set of look-up tables, flip flops, memory blocks, and routing matrices that can be configured, using a hardware description language (HDL) such as VHDL, Verilog, etc., to implement certain logic and memory functions. When using the FPGA to prototype an ASIC design, the HDL can be configured to describe the behaviors of certain logic blocks and memory blocks on the ASIC. A software compiler can compile a program file that includes HDL associated with the logic blocks and memory blocks, and generate a set of low level programming instructions. The low level programming instructions can then configure the set of look-up tables, flip flops, memory blocks, and routing matrices of a FPGA to implement the logic and memory functions of those logic and memory blocks. The configured FPGA can then be operated under a certain operation condition (e.g., being provided with a certain combination of input signals) to generate an output. The output of the FPGA can then be compared with the expected output of the ASIC design. The comparison result can then be used to validate an ASIC design, and to improve the likelihood that that when an ASIC is fabricated according to the design, the fabricated ASIC will generate the expected output under that operation condition.
The inventors here have recognized several technical problems with the conventional method of using FPGA to emulate the behavior of an integrated circuit. For example, under the current state of technologies, the programmable logic blocks in an FPGA cannot be individually, under user control, powered on or powered off (e.g., by selectively decoupling a logic block from a power supply), to emulate the behaviors of an integrated circuit when the power supply to some of the power domains of the integrated circuit are selectively enabled or disabled. For example, referring to FIG. 1B, when an actual ASIC receives a certain combination of logic values of isolation enable signal, reset, and power disable configured to disable the power supply to a certain power domain (e.g., when isolation enable signal and the power disable are logical “one” and the reset is a logical “zero”), the data previously stored in a memory block of that power domain will be erased (and replaced with a specific pattern, such as all “ones” or “zeros”) as a result of being decoupled from the power supply. However, in the case of a FPGA, the content of an emulated memory block will not be erased by selectively decoupling a power domain from the power supply, since FPGA does not enable such a decoupling. As a result, when emulating a scenario where an ASIC power domain transits from a power-off state to a power-on state, the initial data in an emulated memory block in an FPGA, at a time when the power domain is enabled, can be different from the initial data in an ASIC memory block under the same operation condition, which can lead to inaccurate validation and prototyping.